LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mul IS
PORT(
     A,B:in std_logic_vector(3 downto 0);
     P:out std_logic_vector(7 downto 0));
END mul; 
ARCHITECTURE mul_4 OF mul IS
COMPONENT adder4
  PORT(
    a,b:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    cin:IN STD_LOGIC;
    s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    cout:OUT STD_LOGIC);
END COMPONENT; 
signal lk:std_logic_vector(15 downto 1);
signal ss:std_logic_vector(7 downto 0);
signal lkx:std_logic;
BEGIN
    lkx<='0';

    lk(1)<=A(1) and B(0);
    lk(2)<=A(2) and B(0);
    lk(3)<=A(3) and B(0);
    lk(4)<=A(0) and B(1);
    lk(5)<=A(1) and B(1);
    lk(6)<=A(2) and B(1);
    lk(7)<=A(3) and B(1);
    lk(8)<=A(0) and B(2);
    lk(9)<=A(1) and B(2);
    lk(10)<=A(2) and B(2);
    lk(11)<=A(3) and B(2);
    lk(12)<=A(0) and B(3);
    lk(13)<=A(1) and B(3);
    lk(14)<=A(2) and B(3);
    lk(15)<=A(3) and B(3);
    P(0)<=A(0) and B(0);
    mul1:adder4 port map(a(0)=>lk(1),a(1)=>lk(2),a(2)=>lk(3),a(3)=>lkx,
                      b(0)=>lk(4),b(1)=>lk(5),b(2)=>lk(6),b(3)=>lk(7),
                      s(0)=>P(1),s(1)=>ss(0),s(2)=>ss(1),s(3)=>ss(2),
                      cin=>lkx,cout=>ss(3));
    mul2:adder4 port map(a(0)=>ss(0),a(1)=>ss(1),a(2)=>ss(2),a(3)=>ss(3),b(0)=>lk(8),
                      b(1)=>lk(9),b(2)=>lk(10),b(3)=>lk(11),cin=>lkx,
                      s(0)=>P(2),s(1)=>ss(4),s(2)=>ss(5),s(3)=>ss(6),cout=>ss(7));
    mul3:adder4 port map(a(0)=>ss(4),a(1)=>ss(5),a(2)=>ss(6),a(3)=>ss(7),b(0)=>lk(12),
                      b(1)=>lk(13),b(2)=>lk(14),b(3)=>lk(15),cin=>lkx,
                      s(0)=>P(3),s(1)=>P(4),s(2)=>P(5),s(3)=>P(6),cout=>P(7));
END mul_4; 





